1、IPC-2226Sectional Design Standardfor High Density Interconnect(HDI) Printed BoardsASSOCIATION CONNECTINGELECTRONICS INDUSTRIES2215 Sanders Road, Northbrook, IL 60062-6135Tel. 847.509.9700 Fax 847.509.9798www.ipc.orgIPC-2226April 2003A standard developed by IPCCopyright Association Connecting Electro
2、nics Industries Provided by IHS under license with IPCNot for ResaleNo reproduction or networking permitted without license from IHS-,-The Principles ofStandardizationIn May 1995 the IPCs Technical Activities Executive Committee adopted Principles ofStandardization as a guiding principle of IPCs sta
3、ndardization efforts.Standards Should: Show relationship to Design for Manufacturability(DFM) and Design for the Environment (DFE) Minimize time to market Contain simple (simplified) language Just include spec information Focus on end product performance Include a feedback system on use andproblems
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6、ct preclude any member or nonmember of IPC from manufacturing or sell-ing products not conforming to such Standards and Publication, nor shall the existence of suchStandards and Publications preclude their voluntary use by those other than IPC members,whether the standard is to be used either domest
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10、ship is not automatic unless required by the contract. The TAEC recommends the useof the latest revision.Adopted October 6. 1998Why is therea charge forthis standard?Your purchase of this document contributes to the ongoing development of new and updatedindustry standards. Standards allow manufactur
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14、take advantage of this and the many other benefits of IPC membership as well? Formore information on membership in IPC, please visit www.ipc.org or call 847/790-5372.Thank you for your continued support.Copyright 2003. IPC, Northbrook, Illinois. All rights reserved under both international and Pan-A
15、merican copyright conventions.Anycopying, scanning or other reproduction of these materials without the prior written consent of the copyright holder is strictly prohibited andconstitutes infringement under the Copyright Law of the United States.Copyright Association Connecting Electronics Industrie
16、s Provided by IHS under license with IPCNot for ResaleNo reproduction or networking permitted without license from IHS-,-IPC-2226Sectional DesignStandard for HighDensity Interconnect(HDI) Printed BoardsDeveloped by the HDI Design Subcommittee (D-41) of the HDICommittee (D-40) of IPCUsers of this sta
17、ndard are encouraged to participate in thedevelopment of future revisions.Contact:IPC2215 Sanders RoadNorthbrook, Illinois60062-6135Tel 847 509.9700Fax 847 509.9798ASSOCIATION CONNECTINGELECTRONICS INDUSTRIESCopyright Association Connecting Electronics Industries Provided by IHS under license with I
18、PCNot for ResaleNo reproduction or networking permitted without license from IHS-,-This Page Intentionally Left BlankCopyright Association Connecting Electronics Industries Provided by IHS under license with IPCNot for ResaleNo reproduction or networking permitted without license from IHS-,-Acknowle
19、dgmentAny Standard involving a complex technology draws material from a vast number of sources. While the principal membersof the HDI Design Subcommittee (D-41) of the HDI Committee (D-40) are shown below, it is not possible to include allof those who assisted in the evolution of this standard. To e
20、ach of them, the members of the IPC extend their gratitude.HDICommitteeHDI DesignSubcommitteeTechnical Liaison of theIPC Board of DirectorsChairBob NevesMicrotek LaboratoriesChairLionel FullwoodWKK Distribution Ltd.Nilesh S. NaikEagle Circuits Inc.HDI Design SubcommitteeRobyn L. Aagesen, Cisco Syste
21、msInc.David R. Backen, HoneywellAdvanced CircuitsFrank Y. S. Bai, Taiwan PrintedCircuit AssociationStephen Bakke, C.I.D., AlliantTechsystems Inc.Richard W. Barry, AT&S AustriaTechnologieDavid Boggs, Intel CorporationLarry W. Burgess, LaserViaCorporationByron Case, L-3 CommunicationsWennei Chen, TRW
22、Electronics &Technology DivisionDavid J. Corbett, Defense SupplyCenter ColumbusGerhard Diehl, Alcatel SEL AGC. Don Dupriest, Lockheed MartinMissiles and Fire ControlJohn Dusl, Lockheed MartinCraig S. Fosnaugh, C.I.D., RaytheonSystems CompanyCeferino G. Gonzalez, E. I. du Pontde Nemours and Co.Michae
23、l R. Green, Lockheed MartinSpace and Strategic MissilesHue T. Green, Lockheed MartinSpace and Strategic MissilesSamy Hanna, AT&S AustriaTechnologie & SystemtechnikMike Hassebrock, Rockwell CollinsHappy T. Holden, WestwoodAssociatesMichael L. Hook, C.I.D., MotorolaSPSToru Koizumi, Fujikura Ltd.Michae
24、l G. Luke, C.I.D., RaytheonSystems CompanyRene R. Martinez, NorthropGrummanJohn C. Mather, Rockwell CollinsThad C. McMillan, Dell ComputerCorporationLei Mercado, Intel CorporationJohn H. Morton, C.I.D., LockheedMartin CorporationBenny Nilsson, Ericsson RadioSystems ABSteven M. Nolan, C.I.D.+, Silico
25、nGraphics Computer SystemThomas J. Nowak, Nowak &AssociatesDeepak K. Pai, C.I.D.+, GeneralDynamics-Advanced InformationJohn J. Quigley, Jr., Tech CircuitsInc.David Rooke, Research In MotionLimitedDaryl Sato, Intel CorporationKarl A. Sauter, Sun MicrosystemsInc.Kenneth C. Selk, TRW Electronics &Techn
26、ology DivisionLowell Sherman, Defense SupplyCenter ColumbusVern Solberg, Tessera Technologies,Inc.Randal L. Ternes, Boeing PhantomWorksJim Thoren, Hamilton SundstrandDavid A. Vaughan, Taiyo AmericaInc.Nicholas R. Watts, Intel CorporationDaniel Welch, Arlon MEDJohn E. Williams, RaytheonCompanyDavid L
27、. Wolf, Conductor AnalysisTechnologies, Inc.Thomas J. Zanatta, SymbolTechnologies Inc.James A. Zollo, Motorola Inc.April 2003IPC-2226iiiCopyright Association Connecting Electronics Industries Provided by IHS under license with IPCNot for ResaleNo reproduction or networking permitted without license
28、from IHS-,-Table of Contents1SCOPE. 11.1Purpose . 11.2Document Hierarchy . 11.3Presentation . 11.4Interpretation . 11.5Classification of HDI Types . 11.5.1Core Types . 11.5.2HDI Types . 11.6Via Formation . 11.7Design Features . 12APPLICABLE DOCUMENTS. 12.1IPC . 12.2Underwriters Laboratories . 23GENE
29、RAL REQUIREMENTS. 23.1Terms and Definitions . 23.1.1Microvia (Build-Up Via) . 23.1.2Capture Land (Via Top Land) . 23.1.3Target Land (Via Bottom Land) . 23.1.4Stacked Vias . 33.1.5Stacked Microvias . 33.1.6Staggered Vias . 33.1.7Staggered Microvias . 33.1.8Variable Depth Microvia/Via . 33.2Design Tra
30、deoffs . 33.3Design Layout . 53.3.1Design Considerations . 53.4Density Evaluation . 53.4.1Routability Prediction Methods . 53.4.2Design Basics . 64MATERIALS. 84.1Material Selection . 84.1.1HDI Material Options . 84.1.2Designation System . 94.2Application Levels . 114.3Material Description by Type .
31、114.3.1Dielectric Materials . 114.3.2Materials for Conductive Paths (In-Planeor Inter-Plane) . 114.3.3Materials with Dielectric and ConductiveFunctionality . 124.4Copper Foil . 124.4.1Pits, Dents and Pinholes . 124.5Embedded Electronic Components . 124.5.1Embedded Resistors . 124.5.2Embedded Capacit
32、ors . 124.5.3Embedded Inductors . 135MECHANICAL/PHYSICAL PROPERTIES. 135.1HDI Feature Size . 135.1.1Minimum Hole Sizes for Plated-ThroughHole Vias . 135.2Construction Types . 135.2.1HDI Type I Constructions -1 C 0 or 1 C 1 . 135.2.2HDI Type II Constructions -1 C 0 or 1 C 1 . 135.2.3HDI Type III Cons
33、tructions - 2 C 0 . 135.2.4HDI Type IV Constructions - 1 P 0 . 155.2.5Type V Constructions (Coreless) -Using Layer Pairs . 155.2.6Type VI Constructions . 176ELECTRICAL PROPERTIES. 196.1Equivalent Circuitry . 196.2Final Metal Traces . 196.2.1Inductance and Capacitance . 196.2.2High Frequency Performa
34、nce . 217THERMAL MANAGEMENT. 217.1Thermal Management Concerns for BumpInterconnects on HDI . 227.1.1Junction to Case Thermal Models . 237.2Thermal Flow Management Through HDISubstrate . 248COMPONENT AND ASSEMBLY ISSUES. 278.1General Attachment Requirements . 278.1.1Flip Chip Design Considerations .
35、278.1.2Chip Size Standardization . 278.1.3Bump Site Standards . 288.1.4Bump Options . 298.2Chip Scale Design Considerations . 318.2.1Chip Scale Area Arrays (FBGA and FLGA) . 328.2.2Peripheral Leaded Chip Scale Packages(TSOJ and SOC) . 328.3Printed Board Land Pattern Design . 328.4Substrate Structure
36、 Standard Grid Evolution . 328.4.1Footprint Design . 338.4.2Design Guide Checklist . 33IPC-2226April 2003ivCopyright Association Connecting Electronics Industries Provided by IHS under license with IPCNot for ResaleNo reproduction or networking permitted without license from IHS-,-8.4.3Footprint Pop
37、ulation . 339HOLES/INTERCONNECTIONS. 359.1Microvias . 359.1.1Microvia Formation . 369.2Via Interconnect Variations . 379.2.1Stacked Microvias . 379.2.2Stacked Vias . 389.2.3Staggered Microvias . 389.2.4Staggered Vias . 389.2.5Variable Depth Vias/Microvias . 3910GENERAL CIRCUIT FEATUREREQUIREMENTS. 4
38、110.1Conductor Characteristics . 4110.1.1Balanced Conductors . 4110.2Land Characteristics . 4110.3Determining the Number of Conductors . 4110.4Wiring Factor (Wf) . 4110.4.1Localized Escape Calculations . 4110.4.2Wiring Between Tightly Linked Components . 4310.4.3Total Wiring Requirements . 4310.5Via
39、 and Land Density . 4410.6Trade Off Process . 4410.6.1Wiring Factor Process . 4410.6.2Input/Output (I/O) Variables . 4411DOCUMENTATION. 4512QUALITY ASSURANCE. 45FiguresFigure 1-1Color Key . 2Figure 3-1Staggered Via . 3Figure 3-2Staggered Microvias . 3Figure 3-3Package Size and I/O Count . 6Figure 3-
40、4Feature Pitch and Feature Size DefiningChannel Width . 6Figure 3-5Routing and Via Grid for BGA Package . 7Figure 3-6Feature Pitch and Conductor Per ChannelCombinations . 8Figure 4-1PCB-HDI/Microvia Substrate (Application H) . 11Figure 4-2IC Carrier on HDI/Microvia Substrate(Application I) . 11Figur
41、e 4-3BGA Package on MCM-L Substrate UsingHDI-PCB Technology (Application I) . 11Figure 5-1Type I HDI Construction . 15Figure 5-2Type II HDI Construction . 16Figure 5-3Type III HDI Construction (Caution:Unbalanced constructions may result inwarp & twist.) . 16Figure 5-4Type III HDI Construction with
42、StackedMicrovias (Caution: Unbalancedconstructions may result in warp & twist.) . 17Figure 5-5Type III HDI Construction with StaggeredMicrovias (Caution: Unbalancedconstructions may result in warp & twist.) . 17Figure 5-6Type III HDI with Variable Depth Blind Vias . 17Figure 5-7Type IV HDI Construct
43、ion . 18Figure 5-8Coreless Type V HDI Construction . 18Figure 5-9Type VI Construction . 18Figure 6-1Bump Electrical Path (Redistributed Chip) . 20Figure 6-2Final Metal Trace and UnderlyingTraces (Cross Section) . 20Figure 7-1HDI Thermal Path Relationships . 22Figure 7-2Thermal Management of Chip Sca
44、leand Flip Chip Parts Mounted on HDI . 22Figure 7-3Bump Interconnect Equivalent Model . 23Figure 7-4Wire Bond Example . 24Figure 7-5Approximate Thermal Model for Wire Bond . 24Figure 7-6Flip Chip Example . 25Figure 7-7Approximate Thermal Model for Flip Chip . 25Figure 7-8Chip Underfill Example . 25F
45、igure 7-9Approximate Thermal Model forChip Underfill . 25Figure 7-10Thermal Paste Example . 25Figure 7-11Approximate Thermal Model forThermal Paste . 26Figure 7-12Thermal Resistance . 26Figure 7-14Metallic Thermal Properties . 26Figure 7-13Parallel Resistances . 26Figure 8-1Flip Chip Connection . 27
46、Figure 8-2Mechanical and Electrical Connections . 27Figure 8-3Joined Chip and Chip Underfill . 27Figure 8-4Example Layouts . 28Figure 8-5Suggested Direct Chip Attach Grid Pitch(250 m 9,843 in Grid; 150 m5,906 in Bumps) . 30Figure 8-6Type of CSP . 31Figure 8-7Chip Scale Peripheral Package . 32Figure
47、8-8Printed Board Flip Chip or Grid ArrayLand Patterns . 32Figure 8-9MSMT Land Drawing and Dimensions . 33Figure 8-10Standard Grid Structure . 34Figure 8-11Bump Footprint Planning . 34Figure 8-12Redundant Footprint . 34Figure 8-13Design Shrink Footprint . 35Figure 8-14Signal and Power Distribution Po
48、sition . 35Figure 8-15Nested I/O Footprint . 35Figure 9-1Summary of the Manufacturing Processesfor PIDs, Laser and Plasma Methods ofVia Generation . 36Figure 9-2Microvia Manufacturing Processes . 37April 2003IPC-2226vCopyright Association Connecting Electronics Industries Provided by IHS under licen
49、se with IPCNot for ResaleNo reproduction or networking permitted without license from IHS-,-Figure 9-3Cross-Sectional Views of Methods toMake HDI with Microvias . 37Figure 9-4Four Typical Constructions that EmployLasers for Via Generation . 38Figure 9-5Four Typical Constructions UtilizingEtched or M
50、echanically Formed Vias . 38Figure 9-6Commercially Produced PID(Photoimageable Dielectric) Boards . 39Figure 9-7HDI Board that Employs ConductivePastes as Vias . 39Figure 9-8Stacked Microvias . 39Figure 9-9Stacked Vias . 40Figure 9-10Staggered Microvias . 40Figure 9-11Isometric View of Staggered Via
