1、Copyrighted Material !.! PRENTICE ii HALL A Signal lntegrif EngineeJ!s Companion REAL-TIME TEST AND MEASUREMENT AND DESIGN SIMULATION I Test and Measurement Geoff Lawday David Ireland Greg Edlund Forword by Chns Edwards, Editor, lET Elmromrs Systms ond Softwo magazone A Signal Integrity Engineers Co
2、mpanion Real-Time Test and Measurement and Design Simulation Geoff Lawday, David Ireland, and Greg Edlund PRENTICE HALL An 1m print of Pearson Education Upper Saddle River. NJ Boston Indianapolis San Francisco New York Toronto Montreal London Munich Paris Madrid Cape Town Sydney Tokyo Singapore Mexi
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7、grity engineers companion : real-time test and measurement and design simulation I Geoff Lawday. David J.reland. and Greg Edlund. p. em. ISBN-10: 0-13-1860062 (pbk. :all. paper) L SBN-13: 978-0-13-186006-3 I. Electronic apparatus and appliances-Testing. 2. Electronic apparatus and appliances-Design
8、and construction. 3. Signal procesing-Simulation methods. 4. Switching circuits-Reliability. 5. Oscillators. Electric-Testing. T.lreland. David. 195 7- . Title. TK7870.23.L39 2008 621.3822-uc22 2008011981 Copyright 2008 Pearson Educnrion. Inc. All rights reserved. Printed in the Unitd States of Amer
9、ica. This publiction is protected by copyright. and permission must be obtained from the publisher prior to any prohibited reproduction. storage in a retrieval system. or transmission in any form or by any means. electronic. mechanical, photocopying. recording. or li.kewise. For information regardin
10、g permissions. wrile to: Pearson Education. J.nc. Rights and Contracts Department 75 Arlington Street. Suite 300 Boston. MA 02 J 16 Fax: (617) 848-704 7 ISBN-13: 978-0-131-86006-3 ISBN-10: 0-131-86006-2 Text printed in the United States on recycled paper at Courier in Westford. Massachusetts. First
11、printing June 2008 Editor-in-Chief Mark Taub Acquisitions Editor Bernard Goodwin Marketing Manager Curt Johnson Managing Editor Kristy Hart Project Editots Lori Lyons. Andy Beaster Copy Editors Gayle Johnson, Geneil Breeze Indexer Brad Herriman Credits Proofreader Linda K. Seifert Technical Reviewer
12、s Sam Shaw. James Peterson. Andy Marrwick. Mike Resso Publishing Coordinator Michelle Housley Multimedia Developer Dan Scherf Cover Oesiguet Louisa Adair Composition BronkeiJa PubLishing GraphkS Laura Robbins To our wives: Linda, Jane, and Karen Prentice Hall Modern Semiconductor Design Series James
13、 R. Armstrong and F. Gail Gray VHDL Design Representation and Synthesis Mark Gordon Arnold Verilog Digital Computer Design: Algorithms into Hardware Jayaram Bhasker A VHDL Primer, Third Edition Mark D. Birnbaum Essential Electronic Design Automation (EDA) Eric Bogatin Signal Integrity: Simplified Do
14、uglas Brooks Signal Integrity Issues and Printed Circuit Board Design Ken Coffman Real World FPGA Design with Verilog Alfred Crouch Design-for-Test for Digita/ICs and Embedded Core Systems Dennis Derickson and Marcus Muller (Editors) Digital Communications Test and Measurement Greg Edlund Timing Ana
15、lysis and Simulation for Signa/Integrity Engineers Daniel P. Foty MOSFET Modeling with SPICE: Principles and Practice Tom Granberg Handbook of Digital Techniques for High-Speed Design Nigel Horspool and Peter Gorman The ASIC Handbook William K. Lam Hardware Design Verification: Simulation and Formal
16、 Method-Based Approaches Mike Peng Li jitter, Noise, and Signa/Integrity at High-Speed Farzad Nekoogar and Faranak Nekoogar From ASICs to SOCs: A Practical Approach Farzad Nekoogar Timing Verification of Application-Specific Integrated Circuits (ASICs) Samir Palnitkar Design Verification with David
17、Pellerin and Scott Thibault Practical FPGA Programming in C Christopher T. Robertson Printed Circuit Board Designers Reference: Basics Chris Rowen Engineering the Complex SOC Madhavan Swami nathan and A. Ege Engin Power Integrity Modeling and Design for Semiconductors and Systems Wayne Wolf FPCA-Bas
18、ed System Design Wayne Wolf Modern VLSI Design: System-on-Chip Design, Third Edition Bob Zeidman Verilog Designers Library Foreword It is easy to be misled by the rhetoric of the day. Even the world of electronic engineering is not immune. Words and phrases such as digitalization and digi-tal conver
19、gence carry the subtext that you only have to worry about ones and zeroes; that analog is being shown the door by a growing band of electronics designers in their quest to render more into binary logic. But its an illusion. Far from being squeezed out, the word analog is seeping into all areas of el
20、ectronic designs in increasingly subtle and potentially damaging ways. Matters are made even worse by the ease with which digital control can be used to massage and reshape the form of signals. Pre-emphasis is almost trivial to implement in tJ1e circuits that precede a driver. Although this processi
21、ng can improve the ability of a receiver to decode the signal. it can have deleterious effects on other receivers in the vicinity. Worse than that, the interference can depend heavily on the data being transmitted. From that, it is not hard to see how intermittent, apparently random Heisenbugs can p
22、op up during operation and promptly disappear the moment you try to add instrumentation to work out what . . IS go111g wrong. XV xvi Foreword Signal integrity has been a problem for many years but the issues were often isolated to small parts of a system design. Today, all the trends point to signal
23、 cor-ruption getting worse and worse. Switching speeds are going up and the voltages provided on supply rails are going down. But the trends are not all technical. As you can read in the introduction that follows, some of the biggest problems can result from commercial decisions: the pressure to red
24、uce manufacturing costs are pushing designers to consider cheaper components. packages. and substrates; and designers have less time to get the job done. In some markets, such as cellular handsets, companies want to be able to produce variants very quickly. They might be on the shelf for only six to
25、 nine months. Marketing may not know more than six months out whether the design will be a flyer or a dud: All they can do is extlapolate current trends and hope. The closer they define a product to when it is meant to go on sale, the better their chance of getting it right. But that is no help to a
26、n engineering team trying to make the phone work. The core chips may have been designed for a different phone. But a new screen or keyboard, or a switch from a candy-bar to a flip-phone design means that the board layout has to change. And with a small reanangement of the com-ponents on that board,
27、you can suddenly find that the design decisions made by the chjpmakers are at odds with the requirements of the new layout. What was meant to be a quick-turnaround project to create a simple variant of an existing phone for a new market suddenly looks a lot less tractable. In this book, the authors
28、take you through the methods available to digital designers to ensure that they are not vulnerable to the little tricks that the analog properties world can play on them. It is a comprehensive treatment that shows how working in the virtual and real worlds provide a combined methodology for avoiding
29、 signal-integrity problems. It is tempting to think of signal integrity as a subject dominated by black magic techniques. But there is plenty of science to help the time-starved engineer ensure that a high-speed, low-voltage bus wi II work in the final system. This book demonstrates how modeling and
30、 behavioral simulation let the engineer make sensible decisions early on in the project. It covers tricky subjects such as the modeling of transmission lines-a skill that will prove vital in the commg years. Equally importaDt is the ability to work out where things are going wrong in the prototype,
31、and to track down the source of the problem. Chapters on probing, oscilloscope use, and time-domain reflectometry provide practical advice on the best way to look beyond the ones and zeroes the logic is meant. to see into the electromagnetic soup that the real world is made from. Foreword xvii It is
32、 not just about the wired world either: the last chapter concentrates on the wireless world and the challenges ra.ised by new software-defined radio archi-tectures. This is a book that I am sure will be an essential addition to every electronic engineering lab a E-Mail This Page Add BookmarkA Signal
33、 Integrity Engineers Companion: Real-Time Test and Measurement and Design Simulationby Geoff Lawday; David Ireland; Greg EdlundPublisher: Prentice HallPub Date: June 11, 2008Print ISBN-10: 0-13-186006-2 Print ISBN-13: 978-0-13-186006-3 eText ISBN-10: 0-13-714997-2 eText ISBN-13: 978-0-13-714997-1Pag
34、es: 496 Table of ContentsCopyright Prentic Hall Modern Semiconductor Design Series Foreword Preface Acknowledgments About the Authors Chapter 1. Introduction: An Engineers Companion Section 1.1. Life Cycle: The Motivation to Develop a Simulation StrategySection 1.2. Prototyping: Interconnecting High
35、-Speed Digital Signals Section 1.3. Pre-emphasis Section 1.4. The Need for Real-Time Test and Measurement Conclusion Chapter 2. Chip-to-Chip Timing and Simulation Section 2.1. Root Cause Section 2.2. CMOS Latch Section 2.3. Timing Failures Section 2.4. Setup and Hold Constraints Section 2.5. Common-
36、Clock On-Chip Timing Section 2.6. Setup and Hold SPICE Simulations Section 2.7. Timing Budget Section 2.8. Common-Clock IO Timing Section 2.9. Common-Clock IO Timing Using a Standard Load Section 2.10. Limits of the Common-Clock Architecture Section 2.11. Inside IO Circuits Section 2.12. CMOS Receiv
37、er Section 2.13. CMOS Differential Receiver Section 2.14. Pin Capacitance Section 2.15. Receiver Current-Voltage Characteristics Section 2.16. CMOS Push-Pull Driver Section 2.17. Output Impedance Section 2.18. Output Rise and Fall Times Section 2.19. CMOS Current Mode Driver Section 2.20. Behavioral
38、 Modeling of IO Circuits Section 2.21. Behavioral Model for CMOS Push-Pull Driver Section 2.22. Behavioral Modeling Assumptions Section 2.23. Tour of an IBIS Model Section 2.24. IBIS Header Section 2.25. IBIS Pin Table Section 2.26. IBIS Receiver Model Section 2.27. IBIS Driver Model Section 2.28. B
39、ehavioral Modeling Assumptions (Reprise) Section 2.29. Comparison of SPICE and IBIS Models Section 2.30. Accuracy and Quality of IO Circuit Models Conclusion Chapter 3. Signal Path Analysis as an Aid to Signal Integrity Section 3.1. The Transmission Line Environment Section 3.2. Characteristic Imped
40、ance, Reflections, and Signal Integrity Section 3.3. The Reflection Coefficient, Impedance, and TDR Concepts Section 3.4. Looking at Real-World Circuit Characteristics Section 3.5. TDR Resolution Factors Section 3.6. Differential TDR Measurements Section 3.7. Frequency Domain Measurements for SI App
41、lications Conclusion Chapter 4. DDR2 Case Study Section 4.1. Evolution from a Common Ancestor Section 4.2. DDR2 Signaling Section 4.3. Write Timing Section 4.4. Read Timing Section 4.5. Get to Know Your IO Section 4.6. Off-Chip Driver Section 4.7. On-Die Termination Section 4.8. Rising and Falling W
42、aveforms Section 4.9. Interconnect Sensitivity Analysis Section 4.10. Conductor and Dielectric Losses Section 4.11. Impedance Tolerance Section 4.12. Pin-to-Pin Capacitance Variation Section 4.13. Length Variation within a Byte Lane Section 4.14. DIMM Connector Crosstalk Section 4.15. Vref AC Noise
43、and Resistor Tolerance Section 4.16. Slope Derating Factor Section 4.17. Final Read and Write Timing Budgets Section 4.18. Sources of Conservatism Conclusion Chapter 5. Real-Time Measurements: Probing Section 5.1. The Anatomy of a Modern Oscilloscope Probe Section 5.2. A Probing Strategy Section 5.3
44、. Measurement Quality Section 5.4. Defining a Probe Section 5.5. Oscilloscope Probes Section 5.6. Dynamic Range Limitations Section 5.7. Advanced Probing Techniques Section 5.8. Logic Analyzer Probing Conclusion Chapter 6. Testing and Debugging: Oscilloscopes and Logic Analyzers Section 6.1. Fundame
45、ntals of Signal Integrity Section 6.2. Signal Integrity Concepts Section 6.3. Verification Tools: Oscilloscopes URL http:/ Section 6.4. Verification Tools: Logic Analyzers Section 6.5. Combining Analog and Digital Measurements Section 6.6. Eye Diagram Analysis Conclusion Chapter 7. Replicating Real-
46、World Signals with Signal Sources Section 7.1. Observing and Controlling Circuit Behavior Section 7.2. Excitation and Control Section 7.3. Signal-Generation Techniques Section 7.4. Arbitrary Function Generators Section 7.5. The Arbitrary Waveform Generator Section 7.6. Logic Signal Sources Conclusio
47、n Chapter 8. Signal Analysis and Compliance Section 8.1. Standards Framework Section 8.2. High-Performance Tools for Compliance Measurements Section 8.3. Validation and Compliance Measurements Section 8.4. Understanding Serial Architectures Section 8.5. Physical Layer Compliance Testing Section 8.6.
48、 Measurements on Optical Signals Section 8.7. Compliance Measurement Considerations: Analysis Section 8.8. Testing the Serial Link Section 8.9. Probes and Probing Section 8.10. Software Tools Section 8.11. Transmitter Measurement Examples Section 8.12. Impedance and Link Measurements Section 8.13. R
49、eceiver Testing Brings Unique Challenges Section 8.14. Digital Validation and Compliance Section 8.15. Multibus Systems Conclusion Chapter 9. PCI Express Case Study Section 9.1. High-Speed Serial Interfaces Section 9.2. Sensitivity Analysis Section 9.3. Ideal Driver and Lossy Transmission Line Section 9.4. Differential Driver with De-emphasis Section 9.5. Card Impedance Tolerance Section 9.6. 3D Discontinuities Section 9.7. Channel Step Response Section 9.8. Crosstalk Pathology Section 9.9. Crosstalk-Induced Jitter Section 9.10. Channel Characteristics Section 9.11. Sensitivity Analysis Res
