1、 User name: CSU San Diego Book: Jitter, Noise, and Signal Integrity at High-Speed No part of any chapter or book may be reproduced or transmitted in any form by any means without the prior written permission for reprints and excerpts from the publisher of the book or chapter. Redistribution or other
2、 use that violates the fair use privilege under U.S. copyright laws (see 17 USC107) or that otherwise violates these Terms of Service is strictly prohibited. Violators will be prosecuted to the full extent of U.S. Federal and Massachusetts laws. Information Theory Computer Science Mike Peng Li Prent
3、ice Hall Jitter, Noise, and Signal Integrity at High-Speed Copyright An Imprint of Pearson Education Many of the designations used by manufacturers and sellers to distinguish their products are claimed as trademarks. Where those designations appear in this book, and the publisher was aware of a trad
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7、ing-in-Publication Data: Li, Mike Peng. Jitter, noise, and signal integrity at high-speed / Mike Peng Li. p. cm. ISBN 0-13-242961-6 (hardback : alk. paper) 1. TelecommunicationTraffic. 2. High performance computing. I. Title. TK5102.985.L56 2007 621.382dc22 2007036914 Copyright 2008 Pearson Educatio
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9、l, photocopying, recording, or likewise. For information regarding permissions, write to: Pearson Education, Inc. Rights and Contracts Department 501 Boylston Street, Suite 900 Boston, MA 02116 URL http:/ ISBN-13: 978-0-13-242961-0 Text printed in the United States on recycled paper at Courier in We
10、stford, Massachusetts. First printing: November 2007 Credits Editor-in-Chief Mark Taub Publishing Partner Bernard Goodwin Managing Editor Gina Kanouse Project Editor Jovana San Nicolas-Shirley Copy Editor Gayle Johnson Indexer Lisa Stumpf Proofreader Water Crest Publishing Editorial Assistant Michel
11、le Housley Cover Designer Louisa Adair Composition ContentWorks Graphics Jake McFarland Laura Robbins Dedication To Mercia, Eric, George, and my parents. User name: CSU San Diego Book: Jitter, Noise, and Signal Integrity at High-Speed No part of any chapter or book may be reproduced or transmitted i
12、n any form by any means without the prior written permission for reprints and excerpts from the publisher of the book or chapter. Redistribution or other use that violates the fair use privilege under U.S. copyright laws (see 17 USC107) or that otherwise violates these Terms of Service is strictly p
13、rohibited. Violators will be prosecuted to the full extent of U.S. Federal and Massachusetts laws. Information Theory Computer Science Mike Peng Li Prentice Hall Jitter, Noise, and Signal Integrity at High-Speed Prentice Hall Modern Semiconductor Design Series James R. Armstrong and F. Gail Gray VHD
14、L Design Representation and Synthesis Mark Gordon Arnold Verilog Digital Computer Design: Algorithms into Hardware Jayaram Bhasker A VHDL Primer, Third Edition Mark D. Birnbaum Essential Electronic Design Automation (EDA) Eric Bogatin Signal Integrity: Simplified Douglas Brooks Signal Integrity Issu
15、es and Printed Circuit Board Design Ken Coffman Real World FPCA Design with Verilog Alfred Crouch Design-for-Test for Digital ICs and Embedded Core Systems Dennis Derickson and Marcus Mller (Editors) Digital Communications Test and Measurement Greg Edlund Timing Analysis and Simulation for Signal In
16、tegrity Engineers Daniel P. Foty MOSFET Modeling with SPICE: Principles and Practice Tom Granberg Handbook of Digital Techniques for High-Speed Design Nigel Horspool and Peter Gorman The ASIC Handbook William K. Lam URL http:/ Hardware Design Verification: Simulation and Formal Method-Based Approach
17、es Mike Peng Li Jitter, Noise, and Signal Integrity at High-Speed Farzad Nekoogar and Faranak Nekoogar From ASICs to SOCs: A Practical Approach Farzad Nekoogar Timing Verification of Application-Specific Integrated Circuits (ASICs) Samir Palnitkar Design Verification with David Pellerin and Scott Th
18、ibault Practical FPCA Programming in C Christopher T. Robertson Printed Circuit Board Designers Reference: Basics Chris Rowen Engineering the Complex SOC Madhavan Swaminathan and A. Ege Engin Power Integrity Modeling and Design for Semiconductors and Systems Wayne Wolf FPCA-Based System Design Wayne
19、 Wolf Modern VLSI Design: System-on-Chip Design, Third Edition Bob Zeidman Verilog Designers Library User name: CSU San Diego Book: Jitter, Noise, and Signal Integrity at High-Speed No part of any chapter or book may be reproduced or transmitted in any form by any means without the prior written per
20、mission for reprints and excerpts from the publisher of the book or chapter. Redistribution or other use that violates the fair use privilege under U.S. copyright laws (see 17 USC107) or that otherwise violates these Terms of Service is strictly prohibited. Violators will be prosecuted to the full e
21、xtent of U.S. Federal and Massachusetts laws. Information Theory Computer Science Mike Peng Li Prentice Hall Jitter, Noise, and Signal Integrity at High-Speed Preface Moores Law continues to guide the semiconductor technology road map. As the feature size of integrated circuits (ICs) reaches 65 nm t
22、oday, and moves to 45, 32, and 22 nm in the near future, it will give IC systems more functionality and data-handling capability. A complex and functionality-rich system needs fast input/output (I/O) to be efficient. As a result, we see that the I/O speed keeps increasing as the number of transistor
23、s keeps increasing for advanced IC systems. Although decreasing feature size and increasing I/O speed enable better system capability and performance, they also introduce technological challenges. One of the most important challenges is jitter as I/O speed increases, because the unit interval (UI),
24、the total available jitter budget for a link, must decrease accordingly to ensure a reasonable bit error rate (BER) for a link system. Another very important challenge as the feature size decreases is to constrain the power density and power consumption within limits, implying that low-power design
25、is necessary. As a result, noise becomes a critical challenge, because it needs to be reduced for low-power/low-voltage signals to maintain a reasonable signal-to-noise ratio (SNR). When the same channel material is maintained while the data rate increases, the data signal is attenuated and degraded
26、 more due to the same loss channel property and much-increased high-frequency contents associated with the higher data rate. The signal integrity (SI) due to signal attenuation and degradation is manifested by deterministic jitter and noise. Jitter, noise, and SI challenges get magnified when I/O li
27、nk data rate increase is achieved by using the same channel material, a common approach used by most of the high-speed I/O standards for cost-effective considerations. Today, most high-speed I/Os are designed around 5 to 6 Gbps rates for computer-centric applications where copper-based channels are
28、used the most, including standards such as PCI Express II (5 Gbps), Serial ATA III (6 Gbps), and FB DIMM I (3.2, 4.0, and 4.8 Gbps). The next generation of those standards will likely double in data rate and will be at 8 to 12 Gbps rates. For network-centric applications, most current designs are at
29、 8 to 10 Gbps rates, such as Fibre Channel 8x (8.5 Gbps), Gigabit Ethernet (GBE) 10 x (10 Gbps), and SONET OC-192 (10 Gbps), where optical fiber-based channels are used the most. The next generation of network I/O link will likely double or quadruple to 17 to 40 Gbps. At 10 Gbps, the UI is 100 ps, a
30、nd at 40 Gbps, the UI is only 25 ps. To maintain a good BER (10-12), the random jitter in I/O links at those data rates has to be in sub-ps or less, and that is a very daunting and challenging task. It is conceivable that, in the future, the jitter, noise, and SI challenges will become even harder a
31、t higher data rates. In the past 20 years or so, many books have been published on signal integrity. However, the coverage of jitter, noise, and BER is rather brief and narrow in those books. Only two books have been dedicated to jitter, but that was 15 to 17 years ago, and the contents are outdated
32、 in comparison with the todays knowledge and understanding of jitter, noise, and SI. Significant progress had created new theories and algorithms for in jitter, noise, and signal integrity in the past ten years. As far as jitter theorems and analysis, jitter components such as deterministic jitter (
33、DJ) and random jitter (RJ) and associated math models have been developed as a better metric for jitter quantification. On the jitter-tracking part, jitter transfer function has been used extensively to determine outputs and tolerances for jitter, noise, and signaling quantitatively. Statistical sig
34、nal analysis methods based on probability density function (PDF), cumulative distribution function (CDF), and the corresponding convolution operation are replacing the conventional simple, unsophisticated, and less accurate peak-to-peak and RMS metrics. Linear time-invariant (LTI) theorems are used
35、regularly, coupling with the statistical signaling and circuit theorems, to determine jitter, noise, and signaling performance for both the link system and the subsystems within it. At the same time, significant advancements also happened in high-speed networks and computer I/O links in terms of arc
36、hitectures and data rate speed. In general, the architectures developed in those standards are all serial at multiple Gbps, with its clock timing being extracted at the receiver side by a clock recovery circuit (CRC). The CRC also tracks and reduces low-frequency jitter at the receiver input to main
37、tain a good overall BER performance for the receiver or system. Various clock and data recovery methods and circuits have been developed, including ones based on phase-locked loop ( PLL), phase interpolator (PI), and oversampling (OS). Each clock recovery implies a different jitter transfer function
38、 and tracking capability and characteristics. To mitigate or compensate for signal degradation due to the lossy channel, extensive and advanced equalization techniques and circuits have been developed, including linear equalization (LE) and decision feedback equalization (DFE). Accordingly, new theo
39、rems, algorithms, designs, and test methods have been developed to accommodate the emerging challenges imposed by new architectures, data rates, clock recovery, and equalization for the latest multiple-Gbps high-speed I/O links. Innovations and breakthroughs have been developed in the past ten years
40、, including theory, algorithm, methodologies for understanding, modeling, and analyzing jitter, noise, and SI. Link architectures, theory, algorithm, and circuits for mitigating them also have been developed. However, no book has focused on all the latest advancements in jitter, noise, and SI in a s
41、ystematic and cohesive manner. This book was written to fill in this gap. This book intends to give a concurrent, comprehensive, systematic, and in-depth review and discussion of fundamentals of, new theories about, and algorithms on jitter, noise, and SI, as well as their modeling, testing, and ana
42、lysis methodologies within the contexts of clock and I/O link signaling. This book covers important topics such as jitter and noise separation theories and algorithms; jitter transfer functions for output and tolerance; clock and PLL jitter; and modeling, analysis, and testing for the link system, c
43、overing its subsystems of transmitter, receiver, channel, reference clock, and PLL, with emphasis on jitter, noise, and SI aspects. We start Chapter 1 with overview of the basics on jitter, noise, and SI and communication link systems. The root cause mechanisms for various jitter, noise, and SI are
44、discussed and the statistical handling for jitter and noise are introduced. Then, we progress to the discussion on jitter and noise components concept and definition and the rationales on why they are necessary and important. In conclusion, we bring the jitter, and noise, and SI discussion to the fr
45、amework of a communication system. With a big picture introduction on jitter, noise, SI, and link communication system in Chapter 1, we will dive into the details on the necessary and relevant mathematical in Chapter 2. Theories on relevant statistics, stochastic processes for jitter, noise, and SI,
46、 and linear time invariant (LTI) theory for link systems and signaling, and the theory for combining statistics with LTI are introduced in this chapter. In Chapters 3 and 4, we apply the statistical and stochastic theory introduced in Chapter 2 to quantify jitter, noise, SI, and BER in terms of appr
47、opriate PDF and CDF, as well spectrum function of power spectrum density (PSD). In Chapter 3, we give quantitative description for each jitter or noise component in terms of PDF and PSD, along with the relationship between component PDFs to the total PDF, and component PSDs to the total PSD. In Chap
48、ter 4, we discuss jitter and noise jointly in a two-dimensional (2-D) frame. The mathematical representations for the joint PDF of jitter and noise (e.g., eye-contour), and joint jitter and noise CDF (e.g., BER contour) are presented. Chapters 5 and 6 are dedicated to jitter and noise separation to
49、various layers of components. In Chapter 5, we present the jitter separation to its components of deterministic jitter (DJ) and random jitter (RJ) based on jitter PDF or CDF function using the widely used Tailfit method. In Chapter 6, we introduce jitter separation based on real-time function or autocorrelation function of jitter to its first and second layer jitter components of data dependent jitter (DDJ), duty-cycle distortion (DCD), inter-symbol interference (ISI), periodic jitter (PJ), bounded uncorrelated jitter (BUJ), and RJ. Jitter spectrum or PSD estimation via Fourier transformatio
